|Ubiso - IP: DVBS2 - Decoder|
DVB-S2 - Decoder
The UBISO Dual DVB-S2 FEC IP is a low-cost, highly optimized dual DVB-S2 IP targeted for best performance at the smallest area. The preprocessing blocks (mapping I/Q values to LLR values, deinterleaver) and the postprocessing blocks (BCH decoder, BBHEADER extraction,..) are customized to the LDPC decoder architecture. This allows the data to get in and out to the LDPC decoder as quickly as possible, thus exploiting the full capacity of our high performance LDPC decoder. The enhanced LDPC Decoder uses a modified Gauss-Seidel-Aglrotihm resulting in a very low gate count and optimal frequency and therefore making the IP extremely competitive.
We published our DVB-S/S2 IP in the international technical conference
...in throughput and convergence
The Ubiso LDPC Decoder uses a modified Gauss-Seidel Algorithm, capable of calculating any permutations in one clock cycle, even submatrices containing two or more permutations. This increases the throughput and convergence by factor two compared to conventional decoding algorithms. These facts allows us to split the size of the submatrizes from 360 to any required factor. Hence reducing gate count and relaxing the routing congestions.
=> reduced level of parallelism from 360 to 90 check processing units (CPU)s
...in memory requirements
Ubisos LLR compression algorithm reduces the required memory size. The compression as well as the decompression process is completely pipelined, no additional latency time is added. A conventional decoder requires a memory of 1.7 MBits in order to store the extrinsic values, our enhanced compressing algorithms needs only 0.97 MBit!Contact us for more information