Ubiso - IP: DVBS2 - Demodulator

DVB-S/S2 - Demodulator and Controller

The „Channel Macro‟ is meant for use as a front-end demodulator IP within a satellite set-top box IC. Its primary function is to take a baseband analog I and Q signal containing the transponder of interest. Then demodulate, decode (legacy only), and output the resulting bit stream for use by the rest of the set-top. Its primary inputs are digitized baseband I/Q signals. Its primary outputs are an analog AGC signal to control the tuner signal level and a unidirectional dual digital transport data interface carrying decoded DSS or MPEG transport data. Control of the Channel Macro is achieved  either through I2C or Rbus interface. A Diseqc interface controls the LNB and switch circuits.

External blocks are to be connected (Compulsory):

  • The Clock&Reset generator
  • The Power Down logic

External blocks are to be connected (Optional):

  • An DVBS2-Decoder, which decodes the demodulation outputs
    (LDPC Decoder and BCH Decoder) and feeds them back into the Demodulator
  • A GPIO multiplexer in case several channel macro cells are used
  • In case several channel macro cells are used, logical circuitry for I2C‟s SDA (out) and Power Down signals

Block Diagram

DVBS2_Channel_macro_block_diagram

Features

  • Up to three channel macro cells can be safely and easily included into the same IC
  • Modes:
    • Non-Backward Compatible Single Layer Mode (DVB-S2)
    • Backward Compatible Hierarchical mode
    • DVB-S Mode (Demodulation and Decoding)
      • Convolutional decoder, interleaver and reed-solomon decoder
  • Signal processing layer:
    • pilot assisted carrier tracking
    • Integrated, high-performance pi/2-BPSK demodulator and Reed Muller FEC decoder for Frame Header processing (PLSCODE).
    • AGC Control, providing gain error signal for tuner
    • Frequency offset compensation
    • Sampling Timing recovery, resampling IQ channel
    • NBC sync detection
    • Carrier tracking loop
    • DVB-S FEC decoding
    • ...
  • Control Layer
    • Microprocessor
    • I2C, UART and DISeqc interface

New DSP features in 3rd generation IPNEW

  • FFT feature for fast frequency offset detection & blind scan support
  • PL header capture for fast blind scan support
  • Frequency tracker for low symbol rates
  • Improved CTL (carrier tracking loop) control for low SNR modes
  • Large scale decimation filter (in anti-alias filter) for low symbol rates
  • DVB-S sync detection enhanced
  • BPSK modulation for DVB-S added
  • DiSEqC module reworked, SCIF functionality added
  • DVB-CI compliant interface regarding to ETSI EN 50221
  • Microcontroller RAM size reduced to 8kByte
  • AMBA-APB interface added
  • Chip Internal BERT regarding to CCITT recommendation O.151 using PRBS15 and PRBS23
  • I2C cell reworked in order to support tuner specific protocols

Application

By attaching the DVBS2-Decoder (LDPC Decoder + BCH Decoder) you can generate a full DVB-S/S2 compliant system, see

DVBS2_Channel_macro_application

 

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